1. Field of the Invention
The present invention relates to a ferroelectric memory device, and more particularly to a ferroelectric random access memory device fabricated using a ferroelectric material having a perovskite structure to obtain an enhanced reliability when data is read out.
2. Description of the Related Art
As well known, semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices in accordance with whether or not information is lost when power is off. A dynamic random access memory (DRAM), which is a volatile memory, is configured to keep information only in a power-on state even though it has a high operating speed. Such a DRAM also has a drawback in that the consumption of power is excessive because refreshing of data should be carried out at intervals of a certain time in order to prevent data from being lost due to leakage current from a charge transfer transistor coupled to a capacitor. Meanwhile, EEPROMs and flash memories, which are non-volatile memories, have drawbacks of a low operating speed and an excessive power consumption even though data can kept in a power-off state.
On the other hand, a ferroelectric random access memory (FeRAM) has advantages in that they have an operating speed similar to that of DRAMs while exhibiting a reduced power consumption. Such an FeRAM is a non-volatile memory capable of keeping data even in a power-off state, like EEPROMs and flash memories. By virtue of these advantages, such an FeRAM has recently been recognized as a substitutive memory for DRAMs, EEPROMs, flash memories, and other semiconductor memories. In accordance with such a recognition, active research and development have been made for FeRAMs in many companies and research institutes in the world.
Such an FeRAM uses a capacitor made of a ferroelectric film, such as PZT(Pb(Zr,Ti)O.sub.3 or SBT(SrBi.sub.2 Ta.sub.2 O.sub.9), having spontaneous polarization characteristics capable of maintaining a polarization generated in accordance with an application of a certain voltage, even after power is off. Such an FeRAM utilizes the hysteretic characteristic of a ferroelectric depicted in FIG. 1.
Referring to FIG. 1, the ferroelectric is polarized when a voltage V applied to the ferroelectric is increased in a plus (+) direction, so that it exhibits a maximum polarized value Qmax at a maximum voltage. When the applied voltage is cut off, the residual polarization of the ferroelectric corresponds to "Qr". This residual polarization value Qr corresponds to data "1". When the voltage V is decreased in a minus (-) direction, the ferroelectric is polarized in an opposite direction, so that it exhibits a minimum polarized value Qmin at a minimum voltage. When the applied voltage is cut off in this state, the residual polarization of the ferroelectric corresponds to "-Qr". This residual polarization value -Qr corresponds to data "0".
Here, the "+" and "-" directions of the voltage V are indicative of different relative potential relations between the upper and lower electrodes of the capacitor, respectively. The "+", direction means that the upper electrode has a potential relatively higher than that of the lower electrode. The "-" direction means that the upper electrode has a potential relatively lower than that of the lower electrode.
This will be described in more detail, in conjunction with FIG. 5 which is a circuit diagram illustrating the equivalent circuit of a conventional FeRAM. In order to store data "1" in a capacitor of a unit cell UC in the circuit of FIG. 5, a potential, which is higher than that applied to a plate electrode, is applied to a bit line in an ON state of a charge transfer transistor, thereby causing a ferroelectric to be spontaneously polarized. After the spontaneous polarization of the ferroelectric, the charge transfer transistor is turned off, so that data "1" is stored. On the other hand, data "0" is stored by applying, to the bit line, a potential lower than the potential applied to the plate electrode in the ON state of the charge transfer transistor, thereby spontaneously polarizing the ferroelectric, and then turning off the charge transfer transistor.
When data stored in the capacitor is to be read out from the memory, the charge transfer transistor is turned off in a state in which a potential higher than that applied to the plate electrode is applied to the bit line. As a result, a charge dQ1 is discharged into the bit line when the data stored in the capacitor is "1". When the data stored in the capacitor is "0", a charge dQ0 is discharged into the bit line. That is, the potential of the bit line varies in accordance with the value of the data stored in the capacitor because the charge discharged into the bit line varies in accordance with the value of the stored data.
When the data stored in the capacitor is "1", the potential variation V1 of the bit line corresponds to "dQ1/(Cb+Cs)" (V1=dQ1/(Cb+Cs)). On the other hand, the data stored in the capacitor is "0", the potential variation V0 of the bit line corresponds to "dQ0/(Cb+Cs)" (V0=dQ0/(Cb+Cs)). Therefore, it is possible to determine the data ("1" or "0") by comparing the potential of the bit line, outputted at an output terminal (not shown) of the memory, with a reference potential.
The conventional FeRAM shown in FIG. 5 consists of unit cells UC each having a 1T/1C structure including one transistor and one capacitor.
Referring to FIG. 5, the FeRAM includes M.times.N unit cells. Each unit cell UC consists of one transistor (a charge transfer transistor), and one capacitor. The transistor of each unit cell UC is coupled at a gate thereof to an associated one of word lines WL0, WL1, and WL2, at a drain (or a source) thereof to an associated one of bit lines BL0 and BL1, and at a source (a drain) thereof to one end of the capacitor included in the unit cell DC. The other end of the capacitor is connected to an associated one of plate electrode lines PL0, PL1, and PL2. Each bit line BL0 or BL1 is coupled at one end thereof to an associated one of comparators C0 and C1.
The above mentioned conventional FeRAM also includes a reference voltage generating circuit. This reference voltage generating circuit includes two switching transistors ST0 and ST1, and two dummy cells DC0 and DC1. Each of the dummy cells DC0 and DC1 consists of one transistor (a charge transfer transistor), and one capacitor. Respective transistors of the dummy cells DC0 and DC1 are coupled at their drains (or sources) to dummy bit lines DBL and /DBL, and coupled to each other via switching transistors ST0 and ST1 respectively connected to the dummy bit lines DBL and /DBL, thereby forming a common output. The common output from the switching transistors ST0 and ST1 is coupled to the other input of each of the comparators C0 and C1.
That is, each of the comparators C0 and C1 is coupled at one input thereof to an associated one of the bit lines BL0 and BL1, and at the other input thereof to the common output of the dummy bit lines DBL and /DBL. Accordingly, each comparator C0 or C1 determines data ("0" or "1") outputted from an optional unit cell UC by comparing the voltage of the unit cell UC, applied thereto via the associated bit line, with a reference voltage applied thereto from the common output of the switching transistors ST0 and ST1.
Although the conventional FeRAM having the 1T/1C structure has an advantage in terms of a high integration in that it has a small unit cell size, there is a problem in that there may be a RC delay and a drop of the reference voltage because the data determination is carried out by comparing the potential of each bit line with the reference voltage transmitted from the reference voltage generating circuit via an interconnection line having a length different from that of the bit line. Such a problem is a main factor causing errors in the determination of output data.
FIG. 6 is an equivalent circuit diagram illustrating a part of a conventional FeRAM having a 2T/2C structure consisting of two transistors and two capacitors.
The FeRAM shown in FIG. 6 configures each unit cell UC by two transistors (charge transfer transistors) and two capacitors in such a fashion that a reference voltage to be compared with the potential of a bit line adjacent to the unit cell UC is generated from the unit cell UC, as compared to the FeRAM of FIG. 5 including a separate reference voltage generating circuit.
Since each unit cell UC generates a reference voltage to be compared with the potential of a bit line adjacent thereto, the FeRAM having the 2T/2C structure can eliminate the problems involved in the FeRAM having the 1T/1C structure, that is, an RC delayer and a drop of the reference voltage.
However, the FeRAM having the 2T/2C structure has an increased unit cell size because two charge transfer transistors are formed for each unit cell. As a result, this FeRAM has a fatal problem in that it is impossible to achieve a high integration.